 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LOW-COST EMBEDDED ORIONTM RISC MICROPROCESSOR Integrated Device Technology, Inc. IDT79R4640TM IDT79RV4640TM FEATURES * High-performance embedded 64-bit microprocessor - 64-bit integer operations - 64-bit registers - Based on the MIPS RISC Architecture - 80MHz, 100MHz, 133 MHz and 150MHz operation frequency - 32-bit bus interface brings 64-bit power to 32-bit system cost * High-performance DSP capability - 75 Million Integer Mul-Accumulate operations/sec @150MHz - 50 MFlops floating-point operations @150MHz * High-performance microprocessor - 75 M Mul-Add/second @150MHz - 50 MFlops @150MHz - >340,000 dhrystone (2.1)/sec capability @133MHz (197 dhrystone MIPS) * High level of integration - 64-bit, 150 MHz integer CPU - 50MFlops single-precision floating-point unit - 8KB instruction cache; 8KB data cache - Integer multiply unit with 75M Mul-Add/sec * Upwardly software compatible with IDT RISController Family * Easily upgradable to 64-bit system * Low-power operation - Active power management powers-down inactive units - Standby mode * Large, efficient on-chip caches - Separate 8KB Instruction and 8KB Data caches - Over 1800MB/sec bandwidth from internal caches - 2-set associative - Write-back and write-through support - Cache locking to facilitate deterministic response - High performance write protocols for graphics and data communications * Bus compatible with ORION family - System interfaces to 67 MHz, provides bandwidth up to 266 MB/sec - Direct interface to 32-bit wide systems - Synchronized to external reference clock for multimaster operation * Improved real-time support - Fast interrupt decode - Optional cache locking BLOCK DIAGRAM 150 MHz 64-bit ORION CPU 64-bit Register File 64-bit Adder Pipeline Control Load Aligner Store Aligner Logic Unit High-Performance Integer Multiply Exception Management Functions System Control Coprocessor Address Translation/ Cache Attribute Control 50MFlops Single-Precision FPA FP Register File Pipeline Control Pack/Unpack FP Add/Sub/Cvt/ Div/Sqrt FP Multiply Control Bus Data Bus Instruction Bus Instruction Cache Set A (Lockable) 32-bit Synchronized System Interface Data Cache Set A (Lockable) Data Cache Set B Instruction Cache Set B The IDT logo is a registered trademark and ORION, R4650, R4640, RV4640, R4600, R3081, R3052, R3051, R3041, R5000, R36100 , RISController, and RISCore are trademarks of Integrated Device Technology, Inc. COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE (c) 1997 Integrated Device Technology, Inc. MAY 1997 3486/1 1 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE DESCRIPTION The IDT79R4640 is a low-cost member of the Integrated Device Technology, Inc. ORION family, targeted to a variety of performance-hungry embedded applications. The R4640 continues the ORION tradition of highperformance through high-speed pipelines, high-bandwidth caches and bus interface, 64-bit architecture, and careful attention to efficient control. The cost of this performance is reduced by removing functional units frequently not required for many embedded applications. The R4640 supports a wide variety of embedded processor-based applications, such as internetworking equipment (routers, switches), office automation equipment (printers, scanners), and consumer multimedia game systems. Also, being upwardly software-compatible with the RISController family as well as bus- and upwardly software-compatible with the IDT ORION family, the R4640 will serve in many of the same applications. And, the R4640 supports applications that require integer digital signal processing (DSP) functions. The R4640 brings ORION performance levels to lower cost systems. ORION performance is preserved by retaining large on-chip two-way set-associative caches, a streamlined high-speed pipeline, high bandwidth, 64-bit execution, and facilities such as early restart for data cache misses. These techniques allow the system designer over 1.8 GB/sec aggregate internal bandwidth, 266 MB/sec bus bandwidth, almost 200 Dhrystone MIPS, 50MFlops, and 75 M Mul-Add/sec. An array of tools facilitates rapid development of R4640-based systems, allowing a wide Register File variety of customers access to the processor's highThe R4640 has 32 general-purpose 64-bit registers. performance capabilities while maintaining short time-to- These registers are used for scalar integer operations and market goals. address calculation. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. HARDWARE OVERVIEW R4640 is software-compatible with the R4650, and includes the instruction set found in the R4700 microprocessor, targeted at higher performance while maintaining binary compatibility with earlier R30xx processors. The extensions result in better code density, greater multiprocessing support, improved performance for commonly used code sequences in operating system kernels, and faster execution of floating-point intensive applications. All resource dependencies are made transparent to the programmer, insuring transportability among implementations of the MIPS instruction set architecture. In addition, MIPS-III specifies new instructions defined to take advantage of the 64-bit architecture of the processor. Finally, the R4640 also implements additional instructions, which are considered extensions to the MIPS-III architecture. These instructions improve the multiply and multiply-add throughput of the CPU, making it well suited to a wide variety of imaging and DSP applications. These extensions, which use opcodes allocated by MIPS Technologies for this purpose, are supported by a wide variety of development tools. The MIPS integer unit implements a load/store architecture with single cycle ALU operations (logical, shift, add, sub) and autonomous multiply/divide unit. The 64-bit register resources include: 32 general-purpose orthogonal integer registers, the HI/LO result registers for the integer multiply/divide unit, and the program counter. In addition, the on-chip floating-point co-processor adds 32 floating-point registers, and a floating-point control/status register. Some key elements of the R4640 are briefly Arithmetic Logic Unit described below. More detailed information is available in The R4640 ALU consists of the integer adder and the IDT79R4640/IDT79R4650 RISC Processor Hard- logic unit. The adder performs address calculations in ware User's Manual. addition to arithmetic operations; the logic unit performs all of the logic and shift operations. Each unit is highly Pipeline The R4640 uses a 5-stage pipeline that is similar to optimized and can perform an operation in a single pipethe IDT79R3000 and the IDT79R4700 processors. The line cycle. simplicity of this pipeline allows the R4640 to cost less than super-scalar processors and require less power than super-pipelined processors. So, unlike superscalar processors, applications that have large data dependencies or require a great deal of load/stores can still achieve peak performance. Integer Execution Engine The R4640 implements the MIPS-III Instruction Set Architecture, and thus is fully upward compatible with applications running on the earlier generation parts. The Integer Multiply/Divide The R4640 uses a dedicated integer multiply/divide unit, optimized for high-speed multiply and multiplyaccumulate operation. Table 1 shows the performance, expressed in terms of pipeline clocks, achieved by the R4640 integer multiply unit. 2 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE Opcode MULT/U, MAD/U MUL Operand Size 16 bit 32 bit 16 bit 32 bit Latency 3 4 3 4 6 36 68 Repeat 2 3 2 3 5 36 68 Stall 0 0 1 2 0 0 0 D M U L T, DMULTU DIV, DIVU D D I V, DDIVU any any any Table 1: R4640 Integer Multiply Operation The floating-point unit of the R4640 directly implements single-precision floating-point operations, which enables the R4640 to perform functions such as graphics rendering without requiring extensive die area or power consumption. The single-precision unit of the R4640 is directly compatible with the single-precision operation of the R4700, and features the same latencies and repeat rates. The R4640 does not directly implement the doubleprecision operations found in the R4700. However, to maintain software compatibility, the R4640 will signal a trap when a double-precision operation is initiated, allowing the requested function to be emulated in software. Alternatively, the system architect could use a software library emulation of double-precision functions, selected at compile time, to eliminate the overhead associated with trap and emulation. Floating-Point Units The R4640's floating-point execution units perform single precision arithmetic, as specified in IEEE Standard 754. The execution unit is broken into a separate multiply unit and a combined add/convert/divide/square root unit. Overlap of multiply and add/subtract is supported. The multiplier is partially pipelined, allowing a new multiplication instruction to begin every 6 cycles. As in the IDT79R4700, the R4640 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in mission-critical environments, such as ADA, and highly desirable for debugging in any environment. The floating-point unit's operation set includes floatingpoint add, subtract, multiply, divide, square root, conversion between fixed-point and floating-point format, conversion among floating-point formats, and floatingpoint compare. These operations comply with IEEE Standard 754. Double precision operations are not directly supported; attempts to execute double-precision floating point operations, or refer directly to doubleprecision registers, result in the R4640 signalling a "trap" to the CPU, enabling emulation of the requested function. The MIPS-III architecture defines that the results of a multiply or divide operation are placed in the HI and LO registers. The values can then be transferred to the general purpose register file using the MFHI/MFLO instructions. The R4640 adds a new multiply instruction, "MUL", which can specify that the multiply results bypass the "Lo" register and are placed immediately in the primary register file. By avoiding the explicit "Move-from-Lo" instruction required when using "Lo", throughput of multiply-intensive operations is increased. An additional enhancement offered by the R4640 is an atomic "multiply-add" operation, MAD, used to perform multiply-accumulate operations. This instruction multiplies two numbers and adds the product to the current contents of the HI and LO registers. This operation is used in numerous DSP algorithms, and allows the R4640 to cost reduce systems requiring a mix of DSP and control functions. Finally, aggressive implementation techniques feature low latency for these operations along with pipelining to allow new operations to be issued before a previous one has fully completed. Table 1 also shows the repeat rate (peak issue rate), latency, and number of processor stalls required for the various operations. The R4640 performs automatic operand size detection to determine the size of the operand, and implements hardware interlocks to prevent overrun, allowing this high-performance to be achieved with simple programming. Floating-Point Coprocessor The R4640 incorporates an entire single-precision floating-point coprocessor on chip, including a floatingpoint register file and execution units. The floating-point coprocessor forms a "seamless" interface with the integer unit, decoding and executing instructions in parallel with the integer unit. 3 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE Table 2 gives the latencies of some of the floating-point System Control Coprocessor Registers instructions in internal processor cycles. The R4640 incorporates all system control coprocessor (CP0) registers on-chip. These registers provide the path through which the virtual memory Instruction Operation system's address translation is controlled, exceptions are Latency handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache ADD 4 features). In addition, the R4640 includes registers to SUB 4 implement a real-time cycle counting facility, which aids in cache diagnostic testing, assists in data error detection, MUL 8 and facilitates software debug. Alternatively, this timer DIV 32 can be used as the operating system reference timer, and can signal a periodic interrupt. SQRT 31 Table 3 shows the CP0 registers of the R4640. CMP FIX FLOAT ABS MOV NEG LWC1 SWC1 3 4 6 1 1 1 2 1 3 4-7, 10, 20-25, 29, 31 8 9 11 12 13 14 15 16 17 DBound 1 2 IBound DBase Number 0 Name IBase Function Instruction address space base (new in R4640) Instruction address space bound (new in R4640) Data address space base (new in R4640) Data address space bound (new in R4640) Not used Table 2: Floating-Point Operation Floating-Point General Register File The floating-point register file is made up of thirty-two 32-bit registers. These registers are used as source or target registers for the single-precision operations. References to these registers as 64-bit registers (as supported in the R4700) will cause a trap to be signalled to the integer unit. The floating-point control register space contains two registers; one for determining configuration and revision information for the coprocessor and one for control and status information. These are primarily involved with diagnostic software, exception handling, state saving and restoring, and control of rounding modes. BadVAddr Count Compare Status Cause EPC PRId Config CAlg Virtual address on address exceptions Counts every other cycle Generate interrupt when Count = Compare Miscellaneous control/status Exception/Interrupt information Exception PC Processor ID Cache and system attributes Cache attributes for the 8 512MB regions of the virtual address space 18 IWatch Instruction breakpoint virtual address System Control Coprocessor (CP0) 19 DWatch Data breakpoint virtual address The system control coprocessor in the MIPS architecture is responsible for the virtual to physical address 26 ECC Used in cache diagnostics translation and cache protocols, the exception control 27 CacheErr Cache diagnostic information system, and the diagnostics capability of the processor. In 28 TagLo Cache index information the MIPS architecture, the system control coprocessor 30 ErrorEPC CacheError exception PC (and thus the kernel software) is implementation dependent. Table 3: R4640 CPO Registers In the R4640, significant changes in CP0 relative to the R4600 have been implemented. These changes are Operation modes The R4640 supports two modes of operation: user designed to simplify memory management, facilitate mode and kernel mode. debug, and speed real-time processing. Kernel mode operation is typically used for exception handling and operating system kernel functions, including 4 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE CP0 management and access to IO devices. In kernel mode, software has access to the entire address space and all of the co-processor 0 registers, and can select whether to enable co-processor 1 accesses. The processor enters kernel mode at reset, and whenever an exception is recognized. User mode is typically used for applications programs. User mode accesses are limited to a subset of the virtual address space, and can be inhibited from accessing CP0 functions. 0xFFFFFFFF Kernel virtual address space (kseg2) Unmapped, 1.0 GB 0xC0000000 0xBFFFFFFF Uncached kernel physical address space (kseg1) Unmapped, 0.5GB 0xA0000000 0x9FFFFFFF Cached kernel physical address space (kseg0) Unmapped, 0.5GB 0x80000000 0x7FFFFFF the virtual address to form the physical address for that reference. If the address is not within bounds, an exception is signalled. This facility enables multiple user processes in a single physical memory without the use of a TLB. This type of operation is further supported by a number of development tools for the R4640, including real-time operating systems and "position independent code". Kernel mode addresses do not use the base-bounds registers, but rather undergo a fixed virtual to physical address translation. Debug Support To facilitate software debug, the R4640 adds a pair of "watch" registers to CP0. When enabled, these registers will cause the CPU to take an exception when a "watched" address is appropriately accessed. Interrupt Vector The R4640 also adds the capability to speed interrupt exception decoding. Unlike the R4700, which utilizes a single common exception vector for all exception types (including interrupts), the R4640 allows kernel software to enable a separate interrupt exception vector. When enabled, this vector location speeds interrupt processing by allowing software to avoid decoding interrupts from general purpose exceptions. Cache Memory To keep the R4640's high-performance pipeline full and operating efficiently, the R4640 incorporates on-chip instruction and data caches that can each be accessed in a single processor cycle. Each cache has its own 64-bit data path and can be accessed in parallel. The cache subsystem provides the integer and floating-point units with an aggregate bandwidth of over 1800 MB per second at a pipeline clock frequency of 150MHz. The cache subsystem is similar in construction to that found in the R4600, although some changes have been implemented. Table 6 is an overview of the caches found on the R4640. Instruction Cache The R4640 incorporates a two-way set associative onchip instruction cache. This virtually indexed, physically tagged cache is 8KB in size and is parity protected. Because the cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the cache access, thus further increasing performance by allowing these two operations to occur simultaneously. The tag holds a 20-bit physical address and valid bit, and is parity protected. The instruction cache is 64-bits wide, and can be refilled or accessed in a single processor cycle. Instruction fetches require only 32 bits per cycle, for a peak instruction bandwidth of 600MB/sec at 150MHz. Sequential accesses take advantage of the 64-bit fetch to reduce power dissipation, and cache miss refill, can write User virtual address space (useg) Mapped, 2.0GB 0x00000000 Figure 3: Mode Virtual Addressing (32-bit mode) Virtual-to-Physical Address Mapping The 4GB virtual address space of the R4640 is shown in figure 3. The 4 GB address space is divided into addresses accessible in either kernel or user mode (kuseg), and addresses only accessible in kernel mode (kseg2:0). The R4640 supports the use of multiple user tasks sharing common virtual addresses, but mapped to separate physical addresses. This facility is implemented via the "base-bounds" registers contained in CP0. When a user virtual address is asserted (load, store, or instruction fetch), the R4640 compares the virtual address with the contents of the appropriate "bounds" register (instruction or data). If the virtual address is "in bounds", the value of the corresponding "base" register is added to 5 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE 64 bits-per-cycle to minimize the cache miss penalty. The without changing cache contents. line size is eight instructions (32 bytes) to maximize * Writeback. Loads and instruction fetches will first performance. search the cache, reading main memory only if the In addition, the contents of one set of the instruction desired data is not cache resident. On data store operacache (set "A") can be "locked" by setting a bit in a CP0 tions, the cache is first searched to see if the target register. Locking the set prevents its contents from being address is cache resident. If it is resident, the cache overwritten by a subsequent cache miss; refill occurs then contents will be updated, and the cache line marked for only into "set B". later writeback. If the cache lookup misses, the target This operation effectively "locks" time critical code into line is first brought into the cache before the cache is one 4kB set, while allowing the other set to service other updated. instruction streams in a normal fashion. Thus, the benefits * Write-through with write allocate. Loads and instrucof cached performance are achieved, while deterministic tion fetches will first search the cache, reading main real-time response is preserved. memory only if the desired data is not cache resident. On data store operations, the cache is first searched to Data Cache see if the target address is cache resident. If it is resiFor fast, single cycle data access, the R4640 includes dent, the cache contents will be updated and main an 8KB on-chip data cache that is two-way set memory will also be written; the state of the "writeback" associative with a fixed 32-byte (eight words) line size. bit of the cache line will be unchanged. If the cache Table 4 lists the R4640 cache attributes. lookup misses, the target line is first brought into the cache before the cache is updated. Characteristics Instruction Data * Write-through without write-allocate. Loads and 8KB 8KB Size instruction fetches will first search the cache, reading 2-way set associa- 2-way set associamain memory only if the desired data is not cache resiOrganization tive tive dent. On data store operations, the cache is first 32B 32B Line size searched to see if the target address is cache resident. If it is resident, the cache contents will be updated, and vAddr11..0 vAddr11..0 Index the cache line marked for later writeback. If the cache pAddr31..12 pAddr31..12 Tag lookup misses, then only main memory is written. Associated with the Data Cache is the store buffer. n.a. writeback /writethru Write policy When the R4640 executes a Store instruction, this singleread sub-block read sub-block entry buffer gets written with the store data while the tag order order Line transfer order comparison is performed. If the tag matches, then the write sequential write sequential data is written into the Data Cache in the next cycle that entire line first word Miss restart after the Data Cache is not accessed (the next non-load cycle). transfer of The store buffer allows the R4640 to execute a store per-word per-byte Parity every processor cycle and to perform back-to-back stores set A set A without penalty. Cache locking Table 4: R4640 Cache Attributes The data cache is protected with byte parity and its tag is protected with a single parity bit. It is virtually indexed and physically tagged to allow simultaneous address translation and data cache access The normal write policy is writeback, which means that a store to a cache line does not immediately cause memory to be updated. This increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. Software can however select write-through for certain address ranges, using the CAlg register in CP0. Cache protocols supported for the data cache are: * Uncached. Addresses in a memory area indicated as uncached will not be read from the cache. Stores to such addresses will be written directly to main memory, Write buffer Writes to external memory, whether cache miss writebacks or stores to uncached or write-through addresses, use the on-chip write buffer. The write buffer holds up to four address and data pairs. The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory update. For uncached and write-through stores, the write buffer significantly increases performance over the R4000 family of processors. System Interface The R4640 supports a 64-bit system interface that is bus compatible with the R4700 system interface. In addition, the R4640 supports a 32-bit system interface mode, allowing the CPU to interface directly with a lower cost memory system. 6 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE The interface consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit command bus protected with parity. In addition, there are 8 handshake signals and 6 interrupt inputs. The interface has a simple timing specification and is capable of transferring data between the processor and memory at a peak rate of 533MB/sec at 133MHz. Figure 4 shows a typical system using the R4640. In this example two banks of DRAMs are used to supply and accept data with a DDxxDD data pattern. The R4640 clocking interface allows the CPU to be easily mated with external reference clocks. The CPU input clock is the bus reference clock, and can be between 25 and 67MHz (somewhat dependent on maximum pipeline speed for the CPU). An on-chip phase-locked-loop generates the pipeline clock from the system interface clock by multiplying it up an amount selected at system reset. Supported multipliers are values 2 through 8 inclusive, allowing systems to implement pipeline clocks at significantly higher frequency than the system interface clock. System Address/Data Bus The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the R4640 and the rest of the system. It is protected with an 8-bit parity check bus, SysADC. When initialized for 32-bit operation, SysAD can be viewed as a 32-bit multiplexed bus, with 4 parity check bits. The system interface is configurable to allow easier interfacing to memory and I/O systems of varying frequencies. The bus frequency and reference timing of the R4640 are taken from the input clock. The rate at which the CPU transmits data to the system interface is programmable via boot time mode control bits. The rate at which the processor receives data is fully controlled by the external device. Therefore, either a low cost interface requiring no read or write buffering or a faster, high performance interface can be designed to communicate with the R4640. Again, the system designer has the flexibility to make these price/performance trade-offs. System Command Bus The R4640 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates whether the SysAD bus carries an address or data. If the SysAD carries an address, then the SysCmd bus also indicates what type of transaction is to take place (for example, a read or write). If the SysAD carries data, then the SysCmd bus also gives information about the data (for example, this is the last data word transmitted, or the cache state of this data line is clean exclusive). The SysCmd bus is bidirectional to support both processor requests and external requests to the R4640. Processor requests are initiated by the R4640 and responded to by an external device. External requests are issued by an external device and require the R4640 to respond. The R4640 supports single datum (one to eight byte) and 8-word block transfers on the SysAD bus. In the case of a single-datum transfer, the low-order 3 address bits gives the byte address of the transfer, and the SysCmd bus indicates the number of bytes being transferred. The choice of 32- or 64-bit wide system interface dictates whether a cache line block transaction requires 4 double Address Boot ROM DRAM (80ns) Control SCSI ENET 32 Memory I/O Controller RV4640 9 2 11 Figure 4: Typical R4640 System Architecture 7 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE word data cycles or 8 single word cycles, and whether a single data transfer larger than 4 bytes should be broken into two smaller transfers. Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy* are used by an external device to indicate to the R4640 whether it can accept a new read or write transaction. The R4640 samples these signals before deasserting the address on read and write requests. ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses between the processor and an external device. When an external device needs to control the interface, it asserts ExtRqst*. The R4640 responds by asserting Release* to release the system interface to slave state. ValidOut* and ValidIn* are used by the R4640 and the external device respectively to indicate that there is a valid command or data on the SysAD and SysCmd buses. The R4640 asserts ValidOut* when it is driving these buses with a valid command or data, and the external device drives ValidIn* when it has control of the buses and is driving a valid command or data. more write after WrRdy* de-asserts. They still follow the issue rule as R4x00 mode for other writes. External Requests The R4640 responds to requests issued by an external device. The requests can take several forms. An external device may need to supply data in response to an R4640 read request or it may need to gain control over the system interface bus to access other resources which may be on that bus. The following is a list of the supported external requests: * Read Response * Null Boot-Time Options Fundamental operational modes for the processor are initialized by the boot-time mode control interface. The boot-time mode control interface is a serial interface operating at a very low frequency (MasterClock divided by 256). The low-frequency operation allows the initialization information to be kept in a low-cost EPROM; alternatively the twenty-or-so bits could be generated by the system interface ASIC or a simple PAL. Immediately after the V CCOK Signal is asserted, the processor reads a serial bit stream of 256 bits to initialize Non-overlapping System Interface The R4640 requires a non-overlapping system all fundamental operational modes. After initialization is interface, compatible with the R4700. This means that complete, the processor continues to drive the serial clock only one processor request may be outstanding at a time output, but no further initialization bits are read. and that the request must be serviced by an external Boot-Time Modes device before the R4640 issues another request. The The boot-time serial mode stream is defined in Table 5. R4640 can issue read and write requests to an external Bit 0 is the bit presented to the processor when VCCOK is device, and an external device can issue read and write asserted; bit 255 is the last. requests to the R4640. The R4640 asserts ValidOut* and simultaneously Power Management CP0 is also used to control the power management for drives the address and read command on the SysAD and SysCmd buses. If the system interface has RdRdy* or the R4640. This is the standby mode and it can be used to Read transactions asserted, then the processor tristates reduce the power consumption of the internal core of the its drivers and releases the system interface to slave state CPU. The standby mode is entered by executing the WAIT by asserting Release*. The external device can then instruction with the SysAD bus idle and is exited by any interrupt. begin sending the data to the R4640. Figure 5 shows a processor block read request and the external agent read response. The read latency is 4 Standby Mode Operation cycles (ValidOut* to ValidIn*), and the response data The R4640 provides a means to reduce the amount of pattern is DDxxDD. Figure 6 shows a processor block power consumed by the internal core when the CPU write. would otherwise not be performing any useful operations. This is known as "Standby Mode". Write Reissue and Pipeline Write The R4700 and the R4640 implement additional write protocols designed to improve performance. This imple- Entering Standby Mode Executing the WAIT instruction enables interrupts and mentation doubles the effective write bandwidth. The write re-issue has a high repeat rate of 2 cycles per write. enters Standby mode. When the WAIT instruction finishes A write issues if WrRdy is asserted 2 cycles earlier and is the W pipe-stage, if the SysAd bus is currently idle, the still asserted at the issue cycle. If it is not still asserted, internal clocks will shut down, thus freezing the pipeline. the last write re-issues again. Pipelined writes have the The PLL, internal timer, and some of the input pins same 2-cycle per write repeat rate, but can issue one (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. If the conditions are not correct when the 8 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE MasterClock SysAD SysCmd ValidOut ValidIn Addr Read Data0 CData Data1 CData Data6 Data7 CData CEOD RdRdy WrRdy Release Figure 5: R4640 Block Read Request MasterClock SysAD SysCmd ValidOut ValidIn RdRdy WrRdy Release Addr Write Data0 CData Data1 CData Data6 CData Data7 CEOD Figure 6: R4640 Block Write Request 9 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE WAIT instruction finishes the W pipe-stage (i.e. the SysAd Thermal Considerations bus is not idle), the WAIT is treated as a NOP. The R4640 utilizes special packaging techniques to Once the CPU is in Standby Mode, any interrupt, improve the thermal properties of high-speed processors. including the internally generated timer interrupt, will The RV4640 is packaged using cavity-up packaging in a cause the CPU to exit Standby Mode. 128-pin thermally enhanced PQFP package ("DU") with a drop-in heat spreader, for devices with low peak power. The R4640 also utilizes the MQUAD package for higher Mode bit Description power consumption devices (the "MU" package), which is 0 Reserved (must be zero) an all-aluminum package with the die attached to a normal copper lead frame mounted to the aluminum 4s:1 Writeback data rate: casing. 32-bit Due to the heat-spreading effect of the aluminum, the 0W MQUAD package allows for an efficient thermal transfer 1 WWx between the die and the case. The aluminum offers less 2 WWxx internal resistance from one end of the package to the 3 WxWx other, reducing the temperature gradient across the 4 WWxxx 5 WWxxxx package and therefore presenting a greater area for 6 WxxWxx convection and conduction to the PCB for a given temper7 WWxxxxxx ature. Even nominal amounts of air flow will dramatically 8 WxxxWxxx reduce the junction temperature of the die, resulting in 9-15 reserved cooler operation. The MQUAD package is pin and socket compatible with the 128-pin PQFP package. 7:5 Clock multiplier: The R4640 is guaranteed in a case temperature 02 range of 0 to +85 C. The type of package, speed 13 24 (power) of the device, and air flow conditions affect the 35 equivalent ambient temperature conditions that will meet 46 this specification. 57 The equivalent allowable ambient temperature, TA, 68 can be calculated using the thermal resistance from case 7 reserved to ambient (CA) of the given package. The following equation relates ambient and case temperatures: 8 0 Little endian 1 Big endian 10:9 00 R4000 compatible 01 reserved 10 pipelined writes 11 write re-issue Disable the timer interrupt on Int[5] Must be 1 Output driver strength: 10 100% strength (fastest) 11 83% strength 00 67% strength 01 50% strength (slowest) Must be zero TA = TC - P * CA where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device. Typical values for CA at various air flows are shown in Table 6. 11 12 14:13 CA Airflow (ft/min) 128 PQFP (DU) 128 MQUAD (MU) 0 21 21 200 13 13 400 10 10 600 9 9 800 8 8 1000 7 7 255:15 Table 5: Boot-time mode stream Table 6: Thermal Resistance (CA) at Various Airflows Note that the R4640 implements advanced power management to substantially reduce the average power dissipation of the device. This operation is described in the IDT79R4640/ IDT79R4650 RISC Processor Hardware User's Manual. 10 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE DATA SHEET REVISION HISTORY Changes to version dated December 1995: Features: - Added 32-bit bus interface info - Deleted items from low-power operation descriptions. Hardware Overview: - Added detailed descriptions of features. - Changed Boot Time Mode Stream table values for mode bit 12. DC Electrical Characteristics: - The CIN and COUT values have been changed. AC Electrical Characteristics: - In System Interface Parameters tables (R4640 and RV4640), Data Setup and Data Hold minimums changed. Valid Combinations: - List of valid combinations has been corrected. Changes to version dated March 1997: Features: - Added preliminary 150 MHz operation frequency Thermal Considerations: - Added thermally enhanced packaging ("DU") and drop-in heat spreader information. - Upgraded 80 to 133MHz speed grade specs to "final." 11 R4640/RV4640 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION The following is a list of interface, interrupt, and miscellaneous pins available on the R4640. Pin names ending with an asterisk (*) identify pins that are active when low. Pin Name System Bus Interface ExtRqst* Release* RdRdy* WrRdy* ValidIn* Input Output Input Input Input External request Signals that the system interface needs to submit an external request. Release interface Signals that the processor is releasing the system interface to slave state Read Ready Signals that an external agent can now accept a processor read. Write Ready Signals that an external agent can now accept a processor write request. Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. System address/data bus A 32-bit address and data bus for communication between the processor and an external agent. System address/data check bus A 4-bit bus containing parity check bits for the SysAD bus during data bus cycles. System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. Reserved system command/data identifier bus parity For the R4640 this signal is unused on input and zero on output. Type Description ValidOut* Output SysAD(31:0) Input/Output SysADC(3:0) SysCmd(8:0) Input/Output Input/Output SysCmdP Input/Output Clock/Control interface MasterClock Input Master clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization. Quiet VCC for PLL Quiet VCC for the internal phase locked loop. Quiet VSS for PLL Quiet VSS for the internal phase locked loop. VCCP VSSP Input Input 12 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE Pin Name Interrupt interface Int*(5:0) NMI* Type Description Input Input Interrupt Six general processor interrupts, bit-wise OR' d with bits 5:0 of the interrupt register. Non-maskable interrupt Non-maskable interrupt, OR'd with bit 6 of the interrupt register. Initialization interface VCCOk Input VCC is OK When asserted, this signal indicates to the R4640 that the power supply has been above Vcc minimum for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream. Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with MasterClock. Reset This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with MasterClock. Boot mode clock Serial boot-mode data clock output at the system clock frequency divided by 256. Boot mode data in Serial boot-mode data input. ColdReset* Input Reset* Input ModeClock ModeIn Output Input 13 R4640/RV4640 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) R4640 5.0V5% Symbol VTERM TC TBIAS TSTG IIN IOUT Rating Terminal Voltage with respect to GND Operating Temperature(case) Case Temperature Under Bias Storage Temperature DC Input Current DC Output Current Commercial -0.5(2) to +7.0 0 to +85 -55 to +125 -55 to +125 20(3) 50(4) RV4640 3.3V5% Commercial -0.5(2) to +4.6 0 to +85 -55 to +125 -55 to +125 20(3) 50(4) RV4640 3.3V5% Industrial -0.5(2) to +4.6 -40 to +85 -55 to +125 -55 to +125 20(3) 50(4) Unit V C C C mA mA NOTES TO ABSOLUTE MAXIMUM RATING TABLE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts. 3. When VIN < 0V or VIN > VCC 4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. RECOMMENDED OPERATION TEMPERATURE AND SUPPLY VOLTAGE R4640 Grade Commercial Industrial Temperature 0C to +85C (Case) -40 + 85C (Case) GND 0V 0V VCC 5.0V5% N/A RV4640 VCC 3.3V5% 3.3V5% 14 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS -- COMMERCIAL TEMPERATURE RANGE--R4640 (VCC=5.0V 5%; TCASE = 0C to +85C) Clock Parameters--R4640(2) R4640 80MHz Parameter Pipeline clock frequency MasterClock HIGH MasterClock LOW MasterClock Frequency MasterClock Period Clock Jitter for MasterClock MasterClock Rise Time MasterClock Fall Time ModeClock Period Symbol PClk tMCHIGH tMCLOW -- tMCP tJitterIn(1) tMCRise(1) tMCFall(1) tModeCKP(1) Transition tMCHIGH Transition tMCLOW -- -- -- -- -- -- Test Conditions Min 50 6 6 25 25 -- -- -- -- Max 80 -- -- 40 40 250 5 5 256* tMCP R4640 100MHz Min 50 4 4 25 20 -- -- -- -- Max 100 -- -- 50 40 250 5 5 256* tMCP R4640 133MHz Min 50 3 3 25 15 -- -- -- -- Max 133 -- -- 67 40 250 4 4 256* tMCP Units MHz ns ns MHz ns ps ns ns ns NOTES TO R4640/RV4640 AC/DC ELECTRICAL CHARACTERISTIC TABLES: 5. Guaranteed by Design. 6. Operation of the R4640/RV4640 is only guaranteed with the Phase Lock Loop enabled. 7. Timings are measured from 1.5V of the clock to 1.5V of the signal. 8. Capacitive load for all output timings is 50pF. 9. Typical integer instruction mix and cache miss rates. 15 R4640/RV4640 COMMERCIAL TEMPERATURE RANGE System Interface Parameters--R4640 R4640 80MHz Parameter Symbol tDM= Min tDO = Max tDOH* tDS tDH Test Conditions mode14..13 = 10 (fastest) mode14..13 = 01 (slowest) mode14..13 = 10 (fastest) trise = 5ns tfall = 5ns Min 1.0(1) 2.0(1) 1.0 6.5 3 Max 11 15 -- -- -- R4640 100MHz Min 1.0(1) 2.0(1) 1.0 5.5 2 Max 9 12 -- -- -- R4640 133MHz Min 1.0(1) 2.0(1) 1.0 4.5 1.5 Max 9 12 -- -- -- Units ns ns ns ns ns Data Output Data Output Hold Data Setup Data Hold * 25pf loading on external output signals, fastest settings. Boot-Time Interface Parameters--R4640 R4640 80MHz Parameter Mode Data Setup Mode Data Hold Symbol tDS tDH Test Conditions -- -- Min 3 0 Max -- -- R4640 100MHz Min 3 0 Max -- -- R4640 133MHz Min 3 0 Max -- -- Units Master Clock Cycle Master Clock Cycle 16 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS -- COMMERCIAL TEMPERATURE RANGE--R4640 (Vcc = 5.05%, TCASE = 0C to +85C) R4640 80MHz Parameter VOL VOH VOL VOH VIL VIH IIN CIN(1) COUT(1) I/OLEAK Minimum -- VCC - 0.1V -- 3.5V -0.5V 2.0V -- -- -- -- Maximum 0.1V -- 0.4V -- 0.8V VCC + 0.5V 10uA 15pF 15pF 20uA R4640 100MHz Minimum -- VCC - 0.1V -- 2.4V -0.5V 2.0V -- -- -- -- Maximum 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 15pF 15pF 20uA R4640 133MHz Minimum -- VCC - 0.1V -- 2.4V -0.5V 2.0V -- -- -- -- Maximum 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 15pF 15pF 20uA |IOUT|= 4mA -- -- 0 VIN VCC -- -- Input/Output Leakage |IOUT|= 20uA Conditions Power Consumption--R4640 R4640 80MHz Parameter System Condition: -- standby -- 575 mAb 625 mAb active 625 mAb 1100 mAa 125 Typical Max R4640 100MHz Typical Max R4640 133MHz Typical Max Conditions -- CL = 0pF CL = 50pF CL = 0pF No SysAd activity CL = 50pF R4x00 compatible writes, TC = 25oC CL = 50pF Pipelined writes or write re-issue, TC = 25oC 80/40MHz 50 mAb mAb -- -- 100/50MHz 75 mAb 150 mAb -- -- 133/44MHz 100 mAb 200 mAb 800 mAb 1000 mAb 700 mAb 750 mAb 1000 mAb 1200 mAb 950 mAb 1000 mAb 1350 mAb 1550 mAb ICC 750 mAb 1350 mAa 1000 mAb 1650 mAa a. These are the specifications IDT tests to insure compliance. b. These are not tested. They are the result of engineering analysis and are provided for reference only. 17 R4640/RV4640 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS -- COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE--RV4640 (VCC=3.3V 5%; TCASE = 0C to +85C) Clock Parameters--RV4640(2) RV4640 80MHz Parameter Pipeline clock Frequency MasterClock HIGH MasterClock LOW MasterClock Frequency MasterClock Period Clock Jitter for MasterClock MasterClock Rise Time MasterClock Fall Time ModeClock Period Symbol PClk Transition tMCRise/Fall Transition tMCRise/Fall -- Test Conditions Min 50 Max 80 RV4640 100MHz Min 50 Max 100 RV4640 133MHz Min 50 Max 133 RV4640 150MHz Min 50 Max 150 Units MHz tMCHIGH tMCLOW -- 6 -- 4 -- 3 -- 3 -- ns 6 -- 4 -- 3 -- 3 -- ns 20 40 25 50 25 67 25 67 MHz tMCP tJitterIn(1) tMCRise(1) tMCFall(1) tModeCKP(1) -- 25 40 250 20 40 250 15 40 250 15 40 250 ns -- -- -- -- -- ps -- -- 5 -- 5 -- 4 -- 4 ns -- -- 5 -- 5 -- 4 -- 4 ns -- -- 256* tMCP -- 256* tMCP -- 256* tMCP -- 256* tMCP ns Note that operation of the RV4640 is guaranteed only with the Phase Lock Loop enabled. 18 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE System Interface Parameters--RV4640 RV4640 80MHz Parameter Data Output Symbol tDM= Min tDO = Max Test Conditions mode14..13 = 10 (fastest) mode14..13 = 01 (slowest) Data Output Hold tDOH* tDS tDH mode14..13 = 10 (fastest) trise = 3ns tfall = 3ns Min 1.0(1) 2.0(1) Max 11 RV4640 100MHz Min 1.0(1) 2.0(1) Max 9 RV4640 133MHz Min 1.0(1) 2.0(1) Max 9 RV4640 150MHz Min 1.0(1) 2.0(1) Max 9 Units ns 15 12 12 12 ns 1.0 -- 1.0 -- 1.0 -- 1.0 -- ns Data Setup Data Hold 6.5 3 -- -- 5.5 2 -- -- 4.5 1.5 -- -- 4.5 1.5 -- -- ns ns Note: * 25pf loading on external output signals, fastest settings Boot-Time Interface Parameters--RV4640 RV4640 80MHz Parameter Mode Data Setup Mode Data Hold Symbol tDS tDH Test Conditions -- -- Min 3 0 Max -- -- RV4640 100MHz Min 3 0 Max -- -- RV4640 133MHz Min 3 0 Max -- -- RV4640 150MHz Min 3 0 Max -- -- Units Master Clock Cycle Master Clock Cycle 19 R4640/RV4640 COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS -- COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE--RV4640 (Vcc = 3.35%, TCASE = 0C to +85C) RV4640 80MHz Parameter VOL VOH VOL VOH VIL VIH IIN CIN COUT I/OLEAK -- Min Max 0.1V -- RV4640 100MHz Min Max 0.1V -- RV4640 133MHz Min Max 0.1V -- VCC - 0.1V -- 2.4V -0.5V RV4640 150MHz Min Max 0.1V -- 0.4V -- 0.2VCC 10uA -- -- -- 15pF 15pF 20uA -- |IOUT|= 4mA Conditions |IOUT|= 20uA VCC - 0.1V -- -- 2.4V -0.5V 0.7Vcc -- -- -- -- 0.4V -- 0.2Vcc 10uA 15pF 15pF 20uA VCC - 0.1V -- -- 2.4V -0.5V 0.4V -- 0.2VCC 10uA 15pF 15pF 20uA VCC - 0.1V -- -- 2.4V -0.5V 0.4V -- 0.2VCC 10uA 15pF 15pF 20uA VCC + 0.5V 0.7Vcc -- -- -- -- VCC + 0.5V 0.7Vcc -- -- -- -- VCC + 0.5V 0.7Vcc VCC + 0.5V -- 0 VIN VCC -- -- Input/Output Leakage POWER CONSUMPTION--RV4640 RV4640 80MHz Parameter System Condition: standby -- -- active ICC 300 mAb 325 mAb Typical Max RV4640 100MHz Typical Max RV4640 133MHz Typical Max RV4640 150MHz Typical Max Conditions -- CL = 0pF CL = 50pF CL = 0pF No SysAd activity CL = 50pF R4x00 compatible writes, TC = 25oC 350 mAb 450 mAa 400 mAb 450 mAa 500 mAb 575 mAa 550 mAb 625 mAa CL = 50pF Pipelined writes or Write re-issue, TC = 25oC 80/40MHz 40 mAb 90 mAb 350 mAb 375 mAb -- -- 100/50MHz 50 mAb 100 mAb 375 mAb 400 mAb -- -- 133/44MHz 60 mAb 110 mAb 450 mAb 500 mAb -- -- 150/50MHz 60 mAb 110 mAb 500 mAb 550 mAb 350 mAb 375 mAb 400 mAb 450 mAb 450 mAb 500 mAb a. These are the specifications IDT tests to insure compliance. b. These are not tested. They are the result of engineering analysis and are provided for reference only. 20 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE PHYSICAL SPECIFICATIONS - 128-Pin MQUAD/ PQFP J X 45 0 3X 70 L D1 D PIN 1 ID h X 45 0 e C E1 E NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. A2 A SYMBOLS A A1 A2 b C D/E D1/E1 e J h L .68 MIN 3.50 .25 3.17 .30 .13 31.00 27.59 MAX 3.86 .51 3.43 .45 .23 31.40 27.79 TOLERANCES UNLESS OTHERWISE SPECIFIED FRAC DEC ANGLES %%p %%P %%P DATE A1 Integrated Device Technology, Inc. dt 3001 Stender Way, Santa Clara, CA 95054 (408) 492-8333 FAX (408) 727-2328 APPROVALS DRAWN CHECKED AA 11/95 .80 BSC .20 REF .89 REF SCALE 128 LD MQUAD RMKT DWG (.80 LD PITCH, GULLWING) SIZE DRAWING NO. REV N/A A PSC-4054 SHEET OF 1 00 1 DO NOT SCALE DRAWING 21 R4640/RV4640 COMMERCIAL TEMPERATURE RANGE R4640-32 PQFP/MQuad Package Pin-Out N.C. pins should be left floating for maximum flexibility as well as for compatibility with future designs. An asterisk (*) identifies a pin that is active when low. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function N.C. SysCmd2 Vcc Vss SysAD5 WrRdy* ModeClock SysAD6 Vcc Vss SysCmd3 SysAD7 SysCmd4 Vcc Vss SysADC0 SysCmd5 SysAD8 Vcc Vss SysCmd6 SysAD9 Vcc Vss SysCmd7 SysAD10 SysCmd8 Vcc Vss SysAD11 SysCmdP SysAD12 Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Function Vcc Vss SysAD13 SysAD14 Vss Vcc SysAD15 Vss Vcc SysADC1 Vss Vcc MasterClock VssP VccP Vss Vss Vss Vss Vss Vss SysADC3 VccOK Vss Vcc SysAD31 Vss Vcc SysAD30 SysAD29 Reset* Vss Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Function Vcc SysAD28 ColdReset* SysAD27 Vss Vcc N.C. SysAD26 N.C. Vss Vcc SysAD25 Vss Vcc SysAD24 SysADC2 Vss Vcc NMI* SysAD23 Release* Vss Vcc SysAD22 Modein RdRdy* SysAD21 Vss Vcc ExtRqst* SysAD20 ValidOut* Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Function Vcc Vss SysAD19 ValidIn* Vcc Vss SysAD18 Int0* SysAD17 Vcc Vss Int1* SysAD16 Int2* Vcc Vss Int3* SysAD0 Int4* Vcc Vss SysAD1 Int5* SysAD2 Vcc Vss SysCmd0 SysAD3 Vcc Vss SysCmd1 SysAD4 22 R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT79 YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process Blank I Commercial (0C to +85C Case) Industrial (-40C to +85C Case) DU MU 80 100 133 150 4640 128-pin PQFP 128-pin MQUAD 80 MHz PClk 100 MHz PClk 133 MHz PClk 150 MHz PClk ORION Processor for Embedded Systems R RV 5.0+/-5% 3.3+/-5% VALID COMBINATIONS IDT79R4640 - 80, 100, 133MHz IDT79RV4640 - 80, 100, 133, 150MHz IDT79RV4640 - 100,133MHz MQUAD package, Commercial Temperature PQFP package, Commercial Temperature PQFP package, Industrial Temperature 23 |
Price & Availability of IDT79RV4640
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |